drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

5325

#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x1fb4

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4960

#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x1fb4

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2841

#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x1250

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

3069

#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x1250

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

3025

#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x1250

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

578

#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x3250

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

591

#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x3250

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

641

#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x3250

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

641

#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x3250