drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

5333

#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x1fb8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4968

#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x1fb8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2849

#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x1254

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

3077

#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x1254

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

3033

#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x1254

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

582

#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

595

#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

645

#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

645

#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254