drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

5335

#define mmCP_HQD_PQ_CONTROL 0x1fba

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4970

#define mmCP_HQD_PQ_CONTROL 0x1fba

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2851

#define mmCP_HQD_PQ_CONTROL 0x1256

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

3079

#define mmCP_HQD_PQ_CONTROL 0x1256

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

3035

#define mmCP_HQD_PQ_CONTROL 0x1256

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

584

#define mmCP_HQD_PQ_CONTROL 0x3256

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

597

#define mmCP_HQD_PQ_CONTROL 0x3256

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

647

#define mmCP_HQD_PQ_CONTROL 0x3256

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

647

#define mmCP_HQD_PQ_CONTROL 0x3256