drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

5345

#define mmCP_HQD_IQ_TIMER 0x1fbf

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4980

#define mmCP_HQD_IQ_TIMER 0x1fbf

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2861

#define mmCP_HQD_IQ_TIMER 0x125b

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

3089

#define mmCP_HQD_IQ_TIMER 0x125b

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

3045

#define mmCP_HQD_IQ_TIMER 0x125b

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

589

#define mmCP_HQD_IQ_TIMER 0x325b

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

602

#define mmCP_HQD_IQ_TIMER 0x325b

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

652

#define mmCP_HQD_IQ_TIMER 0x325b

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

652

#define mmCP_HQD_IQ_TIMER 0x325b