drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

5343

#define mmCP_HQD_IB_CONTROL 0x1fbe

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4978

#define mmCP_HQD_IB_CONTROL 0x1fbe

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2859

#define mmCP_HQD_IB_CONTROL 0x125a

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

3087

#define mmCP_HQD_IB_CONTROL 0x125a

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

3043

#define mmCP_HQD_IB_CONTROL 0x125a

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

588

#define mmCP_HQD_IB_CONTROL 0x325a

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

601

#define mmCP_HQD_IB_CONTROL 0x325a

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

651

#define mmCP_HQD_IB_CONTROL 0x325a

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

651

#define mmCP_HQD_IB_CONTROL 0x325a