drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

7331

#define mmCP_CE_IB1_BASE_LO 0x20c6

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

6970

#define mmCP_CE_IB1_BASE_LO 0x20c6

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

4827

#define mmCP_CE_IB1_BASE_LO 0x20c6

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

5057

#define mmCP_CE_IB1_BASE_LO 0x20c6

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

5013

#define mmCP_CE_IB1_BASE_LO 0x20c6

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h

373

#define mmCP_CE_IB1_BASE_LO 0x21C6

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

517

#define mmCP_CE_IB1_BASE_LO 0xc0c6

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

530

#define mmCP_CE_IB1_BASE_LO 0xc0c6

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

583

#define mmCP_CE_IB1_BASE_LO 0xc0c6

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

583

#define mmCP_CE_IB1_BASE_LO 0xc0c6