drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

7333

#define mmCP_CE_IB1_BASE_HI 0x20c7

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

6972

#define mmCP_CE_IB1_BASE_HI 0x20c7

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

4829

#define mmCP_CE_IB1_BASE_HI 0x20c7

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

5059

#define mmCP_CE_IB1_BASE_HI 0x20c7

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

5015

#define mmCP_CE_IB1_BASE_HI 0x20c7

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h

372

#define mmCP_CE_IB1_BASE_HI 0x21C7

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

518

#define mmCP_CE_IB1_BASE_HI 0xc0c7

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

531

#define mmCP_CE_IB1_BASE_HI 0xc0c7

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

584

#define mmCP_CE_IB1_BASE_HI 0xc0c7

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

584

#define mmCP_CE_IB1_BASE_HI 0xc0c7