drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

4937

#define mmCPC_INT_STATUS 0x1e55

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4598

#define mmCPC_INT_STATUS 0x1e55

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2595

#define mmCPC_INT_STATUS 0x10b5

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

2865

#define mmCPC_INT_STATUS 0x10b5

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

2799

#define mmCPC_INT_STATUS 0x10b5

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

273

#define mmCPC_INT_STATUS 0x30b5

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

275

#define mmCPC_INT_STATUS 0x30b5

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

306

#define mmCPC_INT_STATUS 0x30b5

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

306

#define mmCPC_INT_STATUS 0x30b5