drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

4935

#define mmCPC_INT_CNTL 0x1e54

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4596

#define mmCPC_INT_CNTL 0x1e54

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2593

#define mmCPC_INT_CNTL 0x10b4

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

2863

#define mmCPC_INT_CNTL 0x10b4

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

2797

#define mmCPC_INT_CNTL 0x10b4

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

264

#define mmCPC_INT_CNTL 0x30b4

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

266

#define mmCPC_INT_CNTL 0x30b4

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

297

#define mmCPC_INT_CNTL 0x30b4

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

297

#define mmCPC_INT_CNTL 0x30b4