drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

4879

#define mmCC_GC_EDC_CONFIG 0x1e38

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4536

#define mmCC_GC_EDC_CONFIG 0x1e38

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2537

#define mmCC_GC_EDC_CONFIG 0x1098

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

2807

#define mmCC_GC_EDC_CONFIG 0x1098

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

741

#define mmCC_GC_EDC_CONFIG 0x3098

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

754

#define mmCC_GC_EDC_CONFIG 0x3098

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

826

#define mmCC_GC_EDC_CONFIG 0x3098

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

826

#define mmCC_GC_EDC_CONFIG 0x3098