drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h

88

#define ixUVD_CGC_MEM_CTRL 0xc0

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h

27

#define ixUVD_CGC_MEM_CTRL 0x00C0

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h

86

#define ixUVD_CGC_MEM_CTRL 0xc0

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h

97

#define ixUVD_CGC_MEM_CTRL 0xc0

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

113

#define ixUVD_CGC_MEM_CTRL 0xc0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h

1509

#define ixUVD_CGC_MEM_CTRL 0x0000

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_offset.h

1984

#define ixUVD_CGC_MEM_CTRL 0x0000

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_offset.h

2319

#define ixUVD_CGC_MEM_CTRL 0x0000

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_offset.h

1646

#define ixUVD_CGC_MEM_CTRL 0x0000

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_offset.h

27

#define ixUVD_CGC_MEM_CTRL 0x0000