drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h

5613

#define ZSC_STATUS__SOC_ACCESS_TRIGGER_STATUS__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_sh_mask.h

10360

#define ZSC_STATUS__SOC_ACCESS_TRIGGER_STATUS__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_sh_mask.h

3557

#define ZSC_STATUS__SOC_ACCESS_TRIGGER_STATUS__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_sh_mask.h

6208

#define ZSC_STATUS__SOC_ACCESS_TRIGGER_STATUS__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h

8147

#define ZSC_STATUS__SOC_ACCESS_TRIGGER_STATUS__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_1_sh_mask.h

8126

#define ZSC_STATUS__SOC_ACCESS_TRIGGER_STATUS__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_sh_mask.h

3988

#define ZSC_STATUS__SOC_ACCESS_TRIGGER_STATUS__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_sh_mask.h

13366

#define ZSC_STATUS__SOC_ACCESS_TRIGGER_STATUS__SHIFT 0x0