drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

6668

#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

6482

#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

6305

#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

29186

#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

8959

#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h

11841

#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x00000000

drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h

5268

#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h

5910

#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h

6512

#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h

6390

#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h

7740

#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_7_sh_mask.h

29668

#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_8_0_sh_mask.h

19752

#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_sh_mask.h

7403

#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_sh_mask.h

7830

#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0