arch/arm64/crypto/sm3-neon-core.S

70

#define W1 v1

arch/riscv/crypto/sm3-riscv64-zvksh-zvkb.S

58

#define W1 v6 // LMUL=2

arch/x86/crypto/sm3-avx-asm_64.S

118

#define W1 %xmm1

drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c

762

#define W1 94

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

741

#define W1 95

lib/crypto/arm/sha1-armv7-neon.S

59

#define W1 q7

lib/crypto/riscv/sha256-riscv64-zvknha_or_zvknhb-zvkb.S

60

#define W1 v3

lib/crypto/riscv/sha512-riscv64-zvknhb-zvkb.S

61

#define W1 v12 // LMUL=2

lib/crypto/sm3.c

169

#undef W1

lib/crypto/sm3.c

67

#define W1(i) (W[i & 0x0f])