drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

6682

#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

6496

#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

6319

#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

29200

#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

8973

#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h

11840

#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h

5267

#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h

5909

#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h

6511

#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h

6389

#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h

7754

#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_7_sh_mask.h

29682

#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_8_0_sh_mask.h

19766

#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_sh_mask.h

7417

#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_sh_mask.h

7844

#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L