drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

6677

#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

6491

#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

6314

#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

29195

#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

8968

#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h

11839

#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0x0000000f

drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h

5286

#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h

5928

#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h

6530

#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h

6408

#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h

7749

#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_7_sh_mask.h

29677

#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_8_0_sh_mask.h

19761

#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_sh_mask.h

7412

#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_sh_mask.h

7839

#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf