drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

7059

#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

6854

#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

6677

#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

29783

#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

9596

#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h

11615

#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x00000018

drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h

5422

#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h

6064

#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h

6668

#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h

6544

#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h

8112

#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_7_sh_mask.h

30265

#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_8_0_sh_mask.h

20245

#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_sh_mask.h

7775

#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_sh_mask.h

8202

#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3