drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

742

#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

744

#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

216

#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

438

#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3192

#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2066

#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3737

#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2796

#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1313

#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1313

#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1309

#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1118

#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2472

#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9