drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

103

#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1565

#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1568

#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3006

#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2114

#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6395

#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7211

#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6228

#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

5405

#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

860

#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1