drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

7048

#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

7143

#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

27236

#define VGT_TF_RING_SIZE__SIZE_MASK 0x0001FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

29757

#define VGT_TF_RING_SIZE__SIZE_MASK 0x0001FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

23269

#define VGT_TF_RING_SIZE__SIZE_MASK 0x0001FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

33610

#define VGT_TF_RING_SIZE__SIZE_MASK 0x0001FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

34639

#define VGT_TF_RING_SIZE__SIZE_MASK 0x0001FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

19899

#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

21206

#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

21133

#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

13339

#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

23263

#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h

12810

#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000ffffL

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

15803

#define VGT_TF_RING_SIZE__SIZE_MASK 0xffff

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

17941

#define VGT_TF_RING_SIZE__SIZE_MASK 0xffff

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

18533

#define VGT_TF_RING_SIZE__SIZE_MASK 0xffff