drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

6888

#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

7140

#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

19856

#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

21163

#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

21090

#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

13296

#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

23220

#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h

12590

#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xffffffffL

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

15837

#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xffffffff

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

17977

#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xffffffff

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

18569

#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xffffffff