drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2765

#define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

118

#define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

3824

#define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

4072

#define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

4111

#define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

3939

#define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

3774

#define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

5278

#define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L