drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

760

#define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

1287

#define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

2911

#define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1736

#define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3372

#define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2425

#define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

3614

#define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

3645

#define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

3566

#define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

3166

#define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

4644

#define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10