drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

659

#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

661

#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

715

#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

1239

#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

2851

#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1856

#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3516

#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2575

#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

3777

#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

3812

#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

3643

#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

3333

#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

4825

#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L