drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

474

#define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3229

#define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2103

#define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3774

#define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2839

#define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1356

#define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1356

#define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1352

#define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1161

#define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2515

#define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L