drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

723

#define UVD_SUVD_CGC_GATE__SRE_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

725

#define UVD_SUVD_CGC_GATE__SRE_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

226

#define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

454

#define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3209

#define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2083

#define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3754

#define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2819

#define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1336

#define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1336

#define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1332

#define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1141

#define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2495

#define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L