drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

736

#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

738

#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

213

#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

435

#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3189

#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2063

#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3734

#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2793

#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1310

#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1310

#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1306

#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1115

#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2469

#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6