drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

735

#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x40

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

737

#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x40

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

232

#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

460

#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3215

#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2089

#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3760

#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2825

#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1342

#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1342

#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1338

#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1147

#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2501

#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L