drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

733

#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x20

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

735

#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x20

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

231

#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

459

#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3214

#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2088

#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3759

#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2824

#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1341

#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1341

#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1337

#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1146

#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2500

#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L