drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

727

#define UVD_SUVD_CGC_GATE__SMP_MASK 0x4

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

729

#define UVD_SUVD_CGC_GATE__SMP_MASK 0x4

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

228

#define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

456

#define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3211

#define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2085

#define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3756

#define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2821

#define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1338

#define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1338

#define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1334

#define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1143

#define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2497

#define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L