drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

451

#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3205

#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2079

#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3750

#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2809

#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1326

#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1326

#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1322

#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1131

#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2485

#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16