drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

476

#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3231

#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2105

#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3776

#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2841

#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1358

#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1358

#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1354

#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1163

#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2517

#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L