drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

725

#define UVD_SUVD_CGC_GATE__SIT_MASK 0x2

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

727

#define UVD_SUVD_CGC_GATE__SIT_MASK 0x2

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

227

#define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

455

#define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3210

#define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2084

#define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3755

#define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2820

#define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1337

#define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1337

#define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1333

#define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1142

#define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2496

#define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L