drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

739

#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x100

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

741

#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x100

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

234

#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

462

#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3217

#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2091

#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3762

#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2827

#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1344

#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1344

#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1340

#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1149

#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2503

#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L