drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

244

#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

472

#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3227

#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2101

#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3772

#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2837

#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1354

#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1354

#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1350

#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1159

#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2513

#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L