drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

224

#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

446

#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3200

#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2074

#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3745

#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2804

#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1321

#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1321

#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1317

#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1126

#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2480

#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11