drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

243

#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

471

#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3226

#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2100

#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3771

#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2836

#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1353

#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1353

#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1349

#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1158

#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2512

#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L