drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

738

#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

740

#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

214

#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

436

#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3190

#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2064

#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3735

#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2794

#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1311

#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1311

#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1307

#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1116

#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2470

#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7