drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

737

#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x80

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

739

#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x80

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

233

#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

461

#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3216

#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2090

#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3761

#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2826

#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1343

#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1343

#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1339

#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1148

#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2502

#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L