drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

473

#define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3228

#define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2102

#define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3773

#define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2838

#define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1355

#define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1355

#define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1351

#define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1160

#define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2514

#define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L