drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

732

#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

734

#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

211

#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

433

#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3187

#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2061

#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3732

#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2791

#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1308

#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1308

#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1304

#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1113

#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2467

#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4