drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

477

#define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3232

#define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2106

#define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3777

#define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2842

#define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1359

#define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1359

#define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1355

#define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1164

#define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2518

#define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L