drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

731

#define UVD_SUVD_CGC_GATE__SDB_MASK 0x10

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

733

#define UVD_SUVD_CGC_GATE__SDB_MASK 0x10

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

230

#define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

458

#define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3213

#define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2087

#define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3758

#define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2823

#define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1340

#define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1340

#define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1336

#define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1145

#define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2499

#define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L