drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

747

#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x1000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

749

#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x1000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

238

#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

466

#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3221

#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2095

#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3766

#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2831

#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1348

#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1348

#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1344

#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1153

#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2507

#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L