drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

475

#define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3230

#define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2104

#define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3775

#define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2840

#define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1357

#define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1357

#define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1353

#define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1162

#define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2516

#define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L