drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

730

#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

732

#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

210

#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

432

#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3186

#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2060

#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3731

#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2790

#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1307

#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1307

#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1303

#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1112

#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2466

#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3