drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

729

#define UVD_SUVD_CGC_GATE__SCM_MASK 0x8

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

731

#define UVD_SUVD_CGC_GATE__SCM_MASK 0x8

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

229

#define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

457

#define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3212

#define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2086

#define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3757

#define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2822

#define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1339

#define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1339

#define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1335

#define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1144

#define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2498

#define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L