drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

744

#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

746

#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

217

#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

439

#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3193

#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2067

#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3738

#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2797

#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1314

#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1314

#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1310

#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1119

#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2473

#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa