drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

743

#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x400

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

745

#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x400

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

236

#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

464

#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3219

#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2093

#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3764

#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2829

#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1346

#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1346

#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1342

#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1151

#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2505

#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L