drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

741

#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x200

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

743

#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x200

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

235

#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

463

#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3218

#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2092

#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3763

#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2828

#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1345

#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1345

#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1341

#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1150

#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2504

#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L